The present invention relates to a semiconductor device having a multilayer metal interconnection structure and a method of manufacturing the same.
In a non-volatile semiconductor memory device having a double gate structure, which is constructed with a floating gate and control gate electrode in a stacking manner, the control gate is used as a word line and a row of a memory array is selected by a signal from the word line. Generally, an end of the word line made of polycrystal silicon is disconnected at a position where no memory cell is present and the other end is connected to the output node of a row decoder. In a non-volatile semiconductor memory device having a double-layer metal interconnection structure, a metal interconnect of a first layer is connected to the word line through a contact hole in an area outside a memory cell region on the side where the word line is connected to the output node of the decoder and a metal interconnect of a second layer is connected to a metal interconnect of the first layer through a via-hole, and a metal interconnect of the second layer is connected to the output node of a row decoder.
The above mentioned interconnects of the first and second layers each are formed by the following steps of: forming a hole in an interlayer insulating film locating on the lower side of each of the interconnects by RIE (reactive ion etching), depositing a metal all over the surface of each interlayer insulating film; and forming a pattern from the metal.
FIG. 1 is a sectional view showing a semiconductor device in a step of manufacture in the case where a metal interconnect of a first layer is formed; thereafter an interlayer insulating film is deposited on the metal interconnect; and then a via-hole is formed in the interlayer insulating film by RIE. In the figure, 61 indicates a metal interconnect of a first layer, 62 indicates an interlayer insulating film formed on the metal interconnect 61, 63 indicates a via-hole formed in the interlayer insulating film 62 by a RIE step, and 64 indicates a mask layer for etching. A metal interconnect 61 of the first layer is used as a word line of a memory cell and a memory cell MC wherein control gate electrode is connected to the metal interconnect 61 is symbolically shown as well.
A metal interconnect 61 of the first layer is charged with electricity by fluctuation of a plasma when the via-hole 63 is formed by etching in the RIE step. Since the metal interconnect 61 of the first layer is connected to the control gate electrode of the memory cell MC, a high voltage is imposed to the control gate electrode of the memory cell.
In the RIE step, a back gate (substrate) is fixedly set at a constant voltage, for example at the ground potential. For this reason, a high voltage is also imposed between the floating gate and the substrate by division based on capacitances between the control gate electrode and floating gate electrode and between the floating gate electrode and the substrate. A gate insulating film present between the floating gate electrode and the substrate is generally thinner than a gate insulating film present between the control gate electrode and floating gate electrode. For this reason, the gate insulating film between the floating gate electrode and substrate has a fear to be subjected to electrical breakdown by having the above mentioned high voltage imposed. The breakdown is thought to be caused by a charging damage due to fluctuation of a plasma during a step of boring the via-hole.
In the future of a non-volatile semiconductor memory device, a gate insulating film is further thinned according to the scaling rule and a plasma density is also in an increasing trend, so that the problems are more conspicuous, as mentioned above.
There has been a problem, heretofore, that, when a hole is formed by a RIE step, said hole being used for connection between metal interconnects of a multilayer structure, a metal interconnect of a lower layer is electrically charged by a charging damage and a gate insulation breakdown of a transistor occurs, wherein the gate electrode of the transistor is connected to the metal interconnect of a lower layer.